Repeated movement burns cycles.
Conventional repeated unicast moves the same payload to each destination lane separately. That can dominate runtime when data is reused across many compute lanes.
Semiconductor RTL IP
Licensable data-movement IP for compute-intensive silicon.
Chipstrate develops verified soft RTL IP for AI, DSP, FPGA, accelerator, and custom SoC systems where data reuse, lane fanout, and predictable integration matter.
7.42x
Replay speedup vs repeated unicast, all-ready
100 MHz
Artix-7 routed timing closure target
0
ILA lane-error bitmap in hardware capture
Focus
Small RTL blocks for specific bottlenecks.
Chipstrate targets narrow, high-value silicon problems where a focused RTL primitive can reduce repeated movement, improve throughput, or simplify accelerator dataflow. The current lead IP is HyperStream Multicast Fabric.
Lead IP
HyperStream Multicast Fabric
A verified SystemVerilog multicast stream fabric for workloads where the same vector, coefficient, activation, or sensor stream must reach many processing lanes.
One ingress, many lane deliveries.
HyperStream accepts one vector beat and fans it out through a registered multicast fabric with independent lane readiness.
Built for reuse-heavy streams.
Target workloads include AI weight broadcast, activation fanout, DSP coefficient distribution, sensor-frame fanout, and scratchpad-to-lane streaming.
Replay Benchmark
Hardware-correlated advantage in the validated replay harness.
In the Artix-7 replay configuration, HyperStream delivered the same 1,024 output words with no lane errors while reducing repeated data movement to a single ingress stream plus parallel fanout.
| Mode | Cycles | Output words | Result |
|---|---|---|---|
| HyperStream all-ready | 69 | 1,024 | 7.42x vs repeated unicast |
| HyperStream phased-ready | 176 | 1,024 | 2.91x vs repeated unicast |
| Repeated unicast baseline | 512 | 1,024 | Reference model |
| Scalar-copy baseline | 1,024 | 1,024 | Reference model |
Validation
Evidence available under non-confidential review.
RTL and simulation
SystemVerilog RTL, self-checking replay harness, Vivado/XSim transcript, and waveform artifacts.
Implementation flow
Vivado synthesis, implementation, routed timing, utilization, routed power estimate, route-status, and bitstream logs.
Physical FPGA evidence
Artix-7 FPGA bring-up with ILA capture data, probe files, result counters, screenshots, and external board evidence.
Integration surfaces
Parameterized core RTL with AXI4-Stream style wrapper and APB-controlled SoC-facing wrapper for evaluation discussions.
Engagement
Non-confidential first, source access later.
01
Non-confidential brief and validation summary.
02
Technical fit review for AI, DSP, FPGA, accelerator, or SoC use cases.
03
NDA and limited evaluation package for qualified counterparties.
Contact
Discuss RTL IP licensing or evaluation.
a.curtis@chipstrate.com
Non-confidential briefs and validation summaries are available for qualified semiconductor IP, custom silicon, and accelerator teams.